工作地点：上海

​Responsibility:
Layout Engineers are responsible for creating circuit layouts (analog custom logic, mixed signal) for our industry-leading SerDes offering. The ideal candidate will have extensive experience with the layout of analog and some high speed custom digital circuits for High Speed Serial IO Interfaces in ASIC applications.  

Applicants must have several years of experience in this area must have experience using the design tools associated with these tasks, preferably Cadence tools, and must be familiar with current CMOS technology generations (32nm and below). 

The layout engineer will direct the floor planning, lead other layout designers with leaf cell and block creation, and integration of analog blocks within the IP block.  

The person should be familiar with learning new tools, methodologies, and technology. 

Requirements:

1. BS in Electrical or Computer Engineering.

2. At least 5 years full-custom analog layout/verification and RC extraction experience.

3. Experiences in Mixed signal/analog/high speed layout，SerDes、AD-DA、PLL，etc.

4. Deep Experience with layout in the Cadence Design Environment. Familiar with Virtuoso XL and physical verification tools (DRC,LVS,DFM,YCD,etc).

5. Experienced with Electro migration and voltage drop analysis.

6. Ability to recognize critical signal nets and reduce parasitics by proper floorplanning/placement

7. Good understanding of advanced semiconductor technology process and device physics.

8. Familiar with ESD/Latch up/antenna and related layout solutions is a plus.

9. Good English skills, communication skills, and willingness to work with a global team.

10. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.